1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, it relates to an electrostatic breakdown protecting device of a semiconductor integrated circuit.
2. Description of the Related Art
FIG. 3 shows a circuit diagram of an electrostatic breakdown protecting device in a semiconductor integrated circuit, and FIG. 4 shows its layout diagram, and FIG. 5 shows a sectional view cut along the line b--b in FIG. 4.
In FIGS. 4 and 5, a protective diode is a PN diode comprising a p-type diffusion layer 403 and an n-type diffusion layer 402a on a p-type semiconductor substrate 401. The p-type diffusion layer 403 is connected to an earth wire via an aluminum wire 409a, and the n-type diffusion layer 402a is connected to an I/O terminal 415 via an aluminum wire 410a. Reference numeral 408 is an interlayer insulating film, and numeral 416 is an electric contact.
A protective bipolar transistor is an NPN bipolar transistor comprising the p-type semiconductor substrate 401 as a base, the n-type diffusion layer 402a as a collector and an n-type diffusion layer 402b as an emitter. The n-type diffusion layer 402a which is a collector region of this transistor is connected to the I/O terminal 415 through the aluminum wire 410a, and the n-type diffusion layer 402b which is an emitter region is connected to the earth wire through an aluminum wire 409b.
An NMOSFET for protection is an n-type LDDMOSFET comprising n-type diffusion layers 402c, 402d and a gate electrode 405 on the p-type semiconductor substrate 401. The n-type diffusion layer 402c which is a source region of this transistor and the gate electrode 405 are connected to the earth wire through an aluminum wire 409c. Furthermore, the n-type diffusion layer 402d which is a drain region is connected to the I/O terminal 415 via an aluminum wire 410b, an input resistor 414 and an aluminum wire 410c. Reference numeral 406 is a gate oxide film, and numeral 407 is a side wall insulating film. Furthermore, numeral 404 is a field oxide film.
In the circuit diagram of FIG. 3 in the case that a voltage such as an electrostatic pulse is applied to an I/O terminal 315 and when current flows into an internal circuit via an input resistor 314, the internal circuit tends to be broken. Therefore, for positive application, a discharge path is formed by a protective bipolar transistor 318 and an NMOSFET 319 for protection, and for negative application, the discharge path is formed by a protective diode 317. Thus, when extraordinary voltage is applied, these protective elements become conductive, so that the voltage is clamped to protect the internal circuit.
That is to say, in the case that an extraordinary voltage pulse which is positive to an earth terminal is applied to the I/O terminal, the voltage of the drain diffusion layer 402d of the NMOSFET for protection and the voltage of the n-type diffusion layer 402a which is the collector region of the protective bipolar transistor rise in the first place. At this time, a breakdown voltage (Vbd) of an avalanche breakdown between the drain and the substrate is lower than a Vbd between the collector and the substrate owing to the function of a gate control diode (GCD) comprising the drain, the gate and the substrate, so that an avalanche occurs between the drain and hence the substrate and a substrate potential in the vicinity of the avalanche rises. Then, a forward direction bias is applied between the source and the substrate, so that a parasitic bipolar comprising the drain of the NMOSFET, the substrate and the source is operated and a voltage between the drain and the source is lowered and then fixed (Vsbmos), whereby the internal circuit is protected If an overvoltage is high and the voltage rise of the terminal further continues, the bipolar is then operated between the collector and the emitter of the protective bipolar transistor, and the voltage is lowered (Vsbbip). At this time, a clamp voltage Vsbbip of the bipolar transistor is lower than a clamp voltage Vsbmos of the MOSFET (Vsbbip&lt;Vsbmos), and most of a discharge current flows through the bipolar transistor, so that the NMOSFET for protection is not broken and does not fail from overvoltage.
In the case that extraordinary voltage pulse which is negative to the earth terminal is applied to the I/O terminal, the protective diode allows the current to flow in a forward direction, so that the internal circuit is protected.
In the above-mentioned conventional example, however, when the voltage is applied to the I/O terminals electrons generated from the protective elements diffuse to the internal element via the substrate, so that these electrons are injected into the gate oxide film of the MOSFET in the internal circuit, whereby the change of characteristics takes place and in the worst case, the MOSFET is broken.
Furthermore, between a p-channel type transistor and an n-channel type transistor of the internal circuit which are close to each other, latch up might be caused by a potential rise of the substrate due to the operation of the protective elements.
In order to avoid these problems, it is necessary to secure a long distance between the protective element and the internal element, and such a construction gives rise to a problem that a useless pattern area is required.
For the purpose of preventing the above-mentioned disadvantage caused by an interaction between the protective circuit and the internal circuit, techniques in which a separation layer is arranged between the protective circuit and the internal circuit have been disclosed in the following two publications, but these techniques have some drawbacks.
The technique disclosed in Japanese Patent Application Laid-open No. 58657/1985 utilizes a bipolar manufacturing technique to separate a diode which is the protective element from the substrate, whereby an influence on the internal circuit can be shut out. However, the protective element comprises the diode alone, and so a clamp performance is poor and a large area is inconveniently required.
The technique disclosed in Japanese Patent Application Laid-open No. 241251/1985 similarly utilizes the bipolar manufacturing technique, but in this technique, a bipolar element which is formed simultaneously with an internal bipolar element is used as the protective element. In consequence, the technique has a drawback that a breakdown resistance of the protective element itself to a surge voltage noticeably deteriorates.
In addition, the above-mentioned conventional example shown in FIGS. 3 to 5 further has the following problem. In the protective bipolar transistor, an impedance of its clamp current route is required to be lowered as much as possible, and hence, the protective bipolar transistor is arranged in the vicinity of a bonding pad. Consequently this area is occupied by the protective bipolar transistor. Therefore, the NMOSFET for protection is arranged so as to be slightly separated from the protective bipolar transistor on a layout. Thus, the positioning relation, i.e., a the arrangement of the NMOSFET for protection and the protective bipolar transistor depends upon a chip layout, so that the operation of the protective bipolar transistor does not work as expected on occasion. Furthermore, the conventional example has a drawback that the operation of the protective bipolar transistor is affected by not only the factor of this chip layout but also characteristics, i.e., an impurity concentration and a fault distribution of the semiconductor substrate.